1. Field
This invention relates generally to a three-dimensional wafer level packaged integrated circuit and, more particularly, to a three-dimensional wafer level packaged integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together, where one of the circuit cells is designated as an active cell and the other circuit cell is designated as an inactive cell to provide circuit yield enhancement through vertical circuit redundancy on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area so as to provide cost savings as a result of wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.
2. Discussion
It is known in the art to provide three-dimensional (3D) wafer-level packaging (WLP) of integrated circuits, such as monolithic micro-wave integrated circuits (MMIC), formed on electrically insulating or semi-insulating substrate wafers. In one wafer-level packaging design, a secondary (cover) wafer is mounted to a primary wafer using bonding rings or fences around the perimeter of each individual circuit so as to provide hermetically sealed cavities in which the integrated circuits are provided. Typically, many active and passive integrated circuits are fabricated on the primary wafer, whereas the secondary wafer serves as a passive substrate to form the WLP cover. The bonded pair of wafers are then diced between the bonding ring perimeters to singulate the individually packaged integrated circuits.
During fabrication of integrated circuits on a common substrate wafer, each of the circuits is tested at some point during the fabrication process by applying suitable electric signals to the circuit through testing probes or the like so as to determine which of the circuits properly operates for a particular application. The testing procedure typically determines that a certain percentage of the integrated circuits are inoperable and as such cannot be used and are ultimately discarded.
It is known in the art to provide horizontal (planar) redundancy when fabricating integrated circuits, where multiple identical circuits are horizontally configured and fabricated on the same substrate wafer. These known redundant circuit fabrication techniques for traditional planar circuits typically involve selectable monolithically processed and adjacently placed copies of the circuit on the same wafer. However, such a redundancy fabrication technique limits the number of unique integrated circuits that can be provided on a single wafer, thus reducing the yield of any particular circuit on such wafer and ultimately increasing cost. In addition, it is known in the art that planar monolithically processed integrated circuits on a common substrate are significantly spatially correlated to each other. In other words, typical fabrication processes result in localized wafer area defects such that if one circuit fails, then the probability of an adjacently processed circuit also failing increases; such that they become less effective as redundant backup circuits.